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Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I 2 C Channels 1 (Continued)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Specifications (Measured at 1.40 V Unless Otherwise Specified)
Maximum I 2 C bus Frequency
Fmax
—
—
1.7
MHz
Propagation Delay
5 V Operation
Side A to side B rising 5
Side A to side B falling 5
Side B to side A rising
Side B to side A falling
3.3 V Operation
Side A to side B rising 5
Side A to side B falling 5
Side B to side A rising
Side B to side A falling
Tphab
Tplab
Tphba
Tplba
Tphab
Tplab
Tphba
Tplba
No bus capacitance,
R1 = 1400,
R2 = 499,
See Figure 2
R1 = 806
R2 = 499
—
—
—
—
—
—
—
—
25
15
20
9.0
28
13
20
10
29
22
30
12
35
18
40
15
ns
ns
ns
ns
ns
ns
ns
ns
Pulse width distortion
No bus capacitance,
5V
Side A low to Side B low 5
Side B low to Side A low
3.3 V
Side A low to Side B low 5
Side B low to Side A low
PWDAB
PWDBA
PWDAB
PWDBA
R1 = 1400,
R2 = 499,
See Figure 2
R1 = 806,
R2 = 499
—
—
—
—
9.0
11
15
11
15
20
22
30
ns
ns
ns
ns
Notes:
1. All voltages are relative to respective ground.
2. V IL < 0.450 V, V IH > 0.780 V.
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I 2 C Bus or SMBus” for additional information.
4. I 2 C ? V (Side A) = I 2 CV OL (Side A) – I 2 CV T (Side A). To ensure no latch-up on a given bus, I 2 C ? V (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5. Side A measured at 0.6 V.
6
Rev. 1.6
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